1. Field of the Invention
The present invention relates to a magnetic shift register memory and an accessing method thereof.
2. Description of Related Art
A magnetic random access memory (MRAM) has advantages of non-volatile, high density, high accessing speed and anti-radiation, etc., which can be used to substitute a conventional semiconductor memory and used for embedded memory applications. The conventional magnetic field writing MRAM device applies metal wires for conducting currents and inducing the magnetic field, so as to switch a free layer of the MRAM. However, as a size of the MRAM decreases, a demagnetizing field effect is quickly increased, and a required write current is greatly increased, so that miniaturization of the MRAM is difficult.
Recently, a spin-torque-transfer (STT) switching technique is provided according to the MRAM technique, which is also referred to as a spin-RAM technique. Such technique is a new generation of magnetic memory writing technique, by which the write current directly flows through a memory cell, and as a size of the memory cell decreases, the required write current accordingly decreases, so that such kind of memory can be perfectly miniaturized. However, such STT switching technique still has disadvantages of inadequate thermal stability of devices, excessive write current, and uncertainty of reliability, etc., resulting in enormous obstacles for mass production of such kind of memory.
In addition, a current-driven domain wall motion theory is gradually disclosed and well developed according to the conventional technique during 1998-2004. U.S. Pat. No. 6,834,005B1 provides a device structure which can greatly improve a data storage capacity of a chip or a hard disk, and the device structure is referred to as a magnetic shift register memory. Such kind of memory has a chance to substitute a current dynamic random access memory (DRAM), a static random access memory (SRAM) and a flash chip, and can even implement a technique of “disk drive on a chip”. Such memory mainly applies a magnetic record disk similar to a hard disk, which is folded in a three-dimensional stack for storing data, in which the current drives a domain wall motion to record information therein. Therefore, an equivalent bit size thereof can be greatly reduced, and an operation speed thereof exceeds that of a solid flash chip and a hard disk.
FIGS. 1A-1C are operational schematic diagrams of a conventional magnetic shift register. A shift register memory 100 includes a bit storage region 35, a bit reservoir region 40, a write device 15 and a read device 20 and a track 11 for storing and moving data. The track 11 of the shift register memory 100 is formed by a magnetic metal material such as ferromagnetic materials of NiFe, and CoFe, etc. The track 11 can be magnetized into a plurality of small magnetic domains 25 and 30. Directions of magnetization vectors of the magnetic domains represent logic values 0 and 1 of the stored information. The track 11 of the shift register memory 100 is serially connected to adjacent tracks. A memory region is separated by one set of the write device 15 and the read device 20, and each of the memory regions includes the bit storage region 35 and the bit reservoir region 40. During a quiescent state for storing information, i.e., a stable state without the current being applied to drive a domain wall motion, data of the memory cells (for example, the magnetic domain 25 represents data 0 and the magnetic domain 30 represents data 1) are sequentially stored in the bit storage region 35. Now, none information is stored in the bit reservoir region 40. The read device 20 of the magnetic shift register memory is connected to the track 11 via a magnetic tunnelling junction (MTJ), and when the sequential bit information is about to be read, a current pulse 45 is input to drive each of the magnetic domains 25 and 30 to generate a domain wall motion (DWM) towards a direction of the electron flow.
FIG. 1B illustrates a transient state, in which the bit information located closest to the read device 20 can be read. In the transient state, the previously read bit information is shifted into the bit reservoir region 40. After all of the bit information stored in the bit storage region 35 is read, all of the bit information is shifted to the bit reservoir region 40. Then, an inverted current pulse 45 is input to shift all of the bit information back to the bit storage region 35. When data is written into the magnetic shift register memory, the magnetic domain to be written is also shifted to a position where the write device 15 is located by inputting the current pulse 45, and now the write device 15 also shifts a stray field of a specific direction to a write position via another writing line according to the Ampere's field or DWM scheme, so that the magnetic domain is switched to a direction of the data to be written. Thereafter, the sequential information of the magnetic domain is shifted back to an original position via the inverted current pulse 45. According to a common knowledge of the memory, the read device 20 is connected to a sense amplifier through a select transistor (which can be a MOS transistor), wherein the transistor occupies a physical area of a Si substrate. Sizes of the magnetic domains 25 and 30 are generally far more smaller than that of the transistor, so that an equivalent bit size of the magnetic shift register memory is mainly determined by the size of the transistor and a number of the bit information (25 and 30) stored in the bit storage region 35 that is controlled by the transistor. Since the magnetic shift register memory includes a plurality of bits, the equivalent bit size can be greatly reduced.
FIG. 2 is a schematic diagram illustrating a mechanism of the magnetic shift register of FIGS. 1A-1C. Referring to FIG. 2, for simplicity's sake, the shift register memory 100 can be extended on a straight track, which includes the bit storage region 35 and the bit reservoir region 40 respectively containing a plurality of the magnetic domains 25 and 30. Assuming in FIG. 2, one bit storage region 35 of the shift register memory 100 records data of four bits that can be shifted to the bit reservoir region 40. FIG. 3 is a schematic diagram illustrating a read mechanism. Referring to FIG. 3, a current pulse 106 is, for example, input to the shift register memory 100, so that the magnetic domains 102 and 104 are shifted, and a reading circuit 108 can read bit data from one of the magnetic domains passing through a position where the reading circuit 108 is located. Data to be written into the magnetic domain can be written by a writing circuit.
Basically, design of the conventional magnetic shift register memory is still not ideal, and the magnetic shift register memory technique is still in an early stage of development, which requires further improvement.
Regarding the aforementioned structure and the read/write mechanism, the memory cells are generally shifted for reading or writing data. After read or write of the data is completed, the memory cells are shifted back to original positions, so that a time for shifting the memory cells back to the original positions is wasted.
FIG. 4 is a schematic diagram illustrating a mechanism of a conventional read operation. Referring to FIG. 4, one clock cycle of a clock signal CLK is, for example, 10 ns. A position of the memory cell is, for example, determined according to an address signal Addr, and an address A1 is activated at a time point 400. Thereafter, a write enable signal WE represented by a compensation signal WE of WE is set to be disabled. An output enable signal (OE) represented by a compensation signal OE of OE is activated within one clock cycle after the address A1 is activated. Meanwhile, after the output enable signal is activated, the domain walls are moved in response to a current pulse (WL pulse). For example, the domain walls are sequentially moved forward for n positions to a buffer region during a time section 404, and are sequentially moved backward for the n positions during a time section 406 to move the memory cells from the buffer region back to original positions thereof. During the time section 404, a burst data to be read contains n bits data. Therefore, regarding a signal DIO on a data input/output pin (DIO pin), data reading is performed at the time point 402, and a read operation is completed during a time section 410. Next, another read operation is completed during a time section 414.
In such magnetic memory structure, besides the selected memory unit is determined according to an address (x, y), one memory unit contains n-bit burst data, which is represented by (z).
FIG. 5 is a schematic diagram illustrating a mechanism of a conventional write operation. Referring to FIG. 5, the operation mechanism thereof is similar to that of FIG. 4, in which waveforms of the write enable signal WE and the output enable signal OE are exchanged, and a write operation is completed during a time section 416, while another write operation is further completed during a time section 418. The domain walls are moved in response to the peripheral current pulse signal (WL pulse). For example, the domain walls are sequentially moved forward for n positions to the buffer region during a time section 420, and are sequentially moved backward for the n positions during a time section 422 to move the memory cells from the buffer region back to the original positions.
The aforementioned conventional read and write operations all require the time section 406 or the time section 422 to move the memory cells back to the original addresses, so that an operation time thereof is increased, and an operation speed thereof is decreased.
How to improve the operation speed is one of the major subjects in research and development of the shift register memory.